In advanced dynamic random access memory (DRAM) technology, an array of cells are formed with field effect transistors (FETs) that exhibit a relatively large “short channel effect” and junction leakage problems due to the dopant diffusion of the source/drain, buried strap, and channel. Generally, to reduce the short channel effect and target threshold voltage (Vt), channel doping concentration is increased. However, the higher doping concentration causes the junction leakage current to increase. There is a significantly large junction leakage issue when the channel doping reaches the maximum allowable doping concentration range (approximately 1018/cm3), which is important for refresh of DRAM cells.
In the conventional trench DRAM structure, more doping concentration than the allowable maximum is required because of the diffusion of the buried strap doping below the channel region and source/drain. Therefore, it is very difficult to shrink or scale-down the conventional planar cell structure without solving the high channel doping concentration problem. In fact, conventional DRAM trench cell structure can be only linearly scaled-down without any structural change. This will meet the maximum channel doping range near the buried strap but no further scaling-down is possible because of the large junction leakage due to the junction punch-through-current.
What is needed is a DRAM cell structure and manufacturing process that offers the ability to significantly scale-down the structure as semiconductor manufacturing technologies advance.